Class 06 : FPGA I/O

FPGA I/O 

• Based on the FPGA family the number of banks will vary.
• Each bank having dedicated power and GND pins.
• All the I/O pins will be powered based on the voltage connected to the particular bank
• Based on the device/peripheral logic connected to the bank . bank voltage will be powered. 
• Ex. DDR2 - 2,5V. DDR3 - 1.5V and device with 1.8V and 3.3V should be connected to the bank powered with those voltage respectively. 
• It is not allowed to connect the device with different voltage level logic with FPGA I/O with different voltage logic.

Single Ended and Differential Signalling: 

• FPGA I/O pins can be configured with single ended and differential signals.
• Signals are named with _P/N can be used as differential signals.
• Fews signals will be IP (input only). It is not allowed to assign a output logic with this pin.

I/O Pins

• I/O pins can be configured as Input or output or tristate. 
• If pin is configured as input, the output logic shouldn't be assigned and vice versa.
• If pin is configured as tri-state means it neither draw a current nor sink it.