Class 07 : Logic Design Process

Logic Design Process:

Synthesis:

Netlist:

Mapping:

Routing:

Programming file:

Logic Design Process by the tool:

• Write the logic in VHDL/Verilog

• Check the syntax.

• Synthesis,placement,routing and generating programming files will be taken care by the software tool provided by Xilinx/Altera.

•  Tool generate the netlist then netlist will be converted in to basic digital elements.

•  Logic elements will be grouped to fit in to the CLB in the placement process.

•  Once placement is done, routing process will make the interconnection between the CLBs.

•  Once routing is complete, the programming file (.bit)will be generated and it will be saved in the  project folder.