Class 08 - VHDL PROGRAMMING - Basic Only

VHDL Programming: 

• VHDL Program having two blocks. Entity and architecture body.
• Entity block includes the input and output ports used in the program.
• Architecture Body includes the logic.

• Entity is keyword. even_detector is program name. 
• The input and output ports is defined under the port function.
• Input/output can be single or multi bit variable.
• Single bit variable defined as std_logic
• Multi bit variable defined as std_logic_vector(X downto 0)
• Input variable defined as keyword in
• Output variable defined as keyword out

• In the port definition,make sure the output variable is not used for input for the logic.
• In such case, the variable should be defined as signal.

• Architecture body having a program (logic). 
• Local signal declarations can be added.
• Program will be written in between begin and end statement.