Class 12 : PWM VHDL Code and Simulation Results

PWM VHDL Code and Simulation Results:

• Period is 4 bit variable that defines the ON+OFF cycle time.
• Duty is 4 bit variable define the ON time.
• Duty value shouldn't exceed the period time.
• Until Duty value the PWM will output hig value (Logic 1)
• (Period-duty) value the PWM will output the low value. (Logic 0)

Simulation results:

• Enter the simulation parameters.(Only input variables).
• Clock, duty and period value.
• First simulation results shows duty cycle of 50/50
• Next image shows the PWM output of 20/80 duty cycle

Scope Output:

• Scope output probed @ the FPGA I/O pins. 
• It shows the PWM output of 80/20 duty cycle.

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