VHDL Programming - Basics
- Above list is keywords in VHDL programming. It will be blue color in the program edition.It is not allowed to use the keyword as variable name.
- Example program. Entity part. x,y are single bit input variable.
- Sum, carry is single bit output variable.
- Architecture Body. Half added logic written.
- VHDL program to deine single bit buffer with enable.
- The variable inside process statement is called sensitive variable.
- Any change happening in the sensitive variable will execute the logic.
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