Xilinx System Generator:
- Add te xilinx system generator in the simulink window.
- Add the ports that connect the simulink environmental variables to the xilinx system generator variables.Without those ports both blocks can't be mixed.
- Select the FPGA device/package
- Select the program - VHDL/Verilog
- Generate the project. Then open the project in Xilinx ISE to generate the Programming file.
If you have any questions please email : miycircuits@gmail.com
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