Switching Regulator Layout Checklist:
1. Plan of the Layout
1.0 Understand the system mechanical and thermal constraints. Save sufficient board real estate/area for power supply in the beginning/planning stage of the big system. Don’t wait to do it as the last step.
1.1 Power supply output capacitors are located physically close to the supply load.
– To minimize impedance between the output capacitors and the fast transient load.
1.2 Locate power supply near cooling fan; ensure good air flow path.
– For optimal cooling of the power supply.
1.3 Ground layer is placed between the power layer and the small signal layer.
– To return the current from the power component layer and to shield sensitive small signal traces from power stage switching noise.
1.4 Highlight the schematic traces to identify high current traces, noisy traces and sensitive small signal traces.
1.5 Decide the components on top and bottom sides of the PCB board. Try to keep all power components on the same side.
2. Power Stage Layout
2.1 Place the power components first. Please them in the way that minimizes the length of the high current flow paths through input capacitors, power FETs, inductors, RSENSE and output capacitors.
– To minimize the PCB impedance and conduction losses on high current paths.
2.2 Have solid, low impedance land patterns for the power components, including capacitors, FETs, diodes, inductors and current sensing resistors. Use large copper plane for VIN, VOUT and GND
– To minimize the trace impedance and power component thermal stress.
2.3 Use thick copper or multiple layers for high current power layers.
– To minimize the PCB conduction loss and reduce thermal stress.
2.4 If it is necessary to route a power trace to another layer, choose a trace in low di/dt paths and use multiple vias for interconnection.
– To minimize noise propagation and connection impedance between layers.
2.5 Minimize the pulsating current loop area.
– To minimize the pulsating loop (hot loop) inductance and absorb switching noise.
2.6 Minimize and isolate/shield the high dv/dt SW node areas.
– To minimize the EMI noise source from the high dv/dt SW nodes.
2.7 Separate input current paths among supplies if there is more than one supply on the same input rail and the supplies are not synchronized. Have local input decoupling capacitor for each supply.
– To avoid common impedance noise coupling among supplies.
2.8 PolyPhase converter. Try to have symmetric layout for each phase. Have local ceramic decoupling capacitor for each phase.
3. Control Circuit Layout
3.1 Locate the control circuitry in a quiet location that is close to output capacitors or input capacitors.
– To minimize the noise to the control circuitry.
3.2 Use a separate SGND ground island for the components to the following small signal pins:
– To minimize the noise to the control circuitry.
3.3 Use PGND for power.
3.4 Has a single connection point between SGND and PGND. One suggested location is underneath the IC.
– To minimize SGND noise and provide low impedance gate driver current return path.
3.5 To minimize the connection impedance and provide best noise decoupling with HF capacitors.
3.6 Current sensing traces – Kelvin sensing is required with closely routed sense signals
3.7 Remote voltage sensing traces should be routed together with a pair of traces.
– To minimize the noise and sensing error.
3.8 Gate driver traces – TG and SW traces should be routed together with minimum loop area minimize the noise source from the high dv/dt gate driver traces.
3.9 Maintain distance between sensitive small signal traces and noisy traces/planes.
– To minimize the capacitive noise coupling between noisy traces and small signal traces.
3.10 Trace width –Maintain the trace width as required.
– To minimize the trace impedance.
Source: Linear
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