Switching Regulator - Part 9

Switching Regulator Design: 

Buck Converter:

Selection of PWM controller and parameters:

• Input voltage range -Design input supply.
• RT/CLK - Switching frequency and design requirement on Ripple/noise 
• Enable Pin - Design requirement on power sequencing
• Soft start - Design requirement on power sequencing and reset release.
• Vsense - Design requirement on output voltage level.
• Power Good - Interface to other circuit or indicator

Design:

Input voltage range - 3.5 V to 60V

RT/CLK:

The switching frequency of the TPS54160A is adjustable over a wide range from approximately 100kHz to 2500kHz by placing a resistor on the RT/CLK pin. The RT/CLK pin voltage is typically 0.5V and must have a resistor to ground to set the switching frequency.

Soft start

The slow start capacitor determines the minimum amount of time it will take for the output voltage to reach its nominal programmed value during power up. This is useful if a load requires a controlled voltage slew rate. This is also used if the output capacitance is large and would require large amounts of current to quickly charge the capacitor to the output voltage level.

The slow start time must be long enough to allow the regulator to charge the output capacitor up to the output voltage without drawing excessive current.

Enable Pin:

Many of the common power supply sequencing methods can be implemented using the SS/TR, EN and PWRGD pins. The sequential method can be implemented using an open drain output of a power on reset pin of another device.

The power good is coupled to the EN pin on the device which enables the second power supply once the primary supply reaches regulation. If needed, a 1nF ceramic capacitor on the EN pin of the second power supply provides a desired start-up delay.

Vsense:

The output voltage is set with a resistor divider from the output node to the VSENSE pin. It is recommended to use 1% tolerance or better divider resistors.To improve efficiency at light loads consider using larger value resistors. If the values are too high, the regulator becomes more susceptible to noise and voltage errors from the VSENSE input current are noticeable.

POWER Good:

In general the PWRGD pin is an open drain output. It can be active low or active high output. 

Once the VSENSE pin is between 94% and 107% of the internal voltage reference the PWRGD pin is de-asserted and the pin floats. It is recommended to use a pull-up resistor between the values of 10 and 100kΩ to a voltage source that is 5.5V or less. The PWRGD is in a defined state once the VIN input voltage is greater than 1.5V but with reduced current sinking capability. The PWRGD will achieve full current sinking capability as VIN input voltage approaches 3V. 

The PWRGD pin is pulled low when the VSENSE is lower than 92% or greater than 109% of the nominal internal reference voltage. Also, the PWRGD is pulled low, if the UVLO or thermal shutdown are asserted or the EN pin pulled low.

Source:TI

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