Job Opening: Embedded Development Engineer

Job Opening: Embedded Development Engineer:

Link :https://goo.gl/5nt1zr

Class 13 - Multiphase PWM - Boost Converter Control

Boost Converter Circuit:

Typical boost converter circuit with FPGA PWM control:

• In the closed loop, ADC access and PID controller should be implemented inside the FPGA. 
• PID controller should adjust the PWM duty to control the output voltage @ desired level
• The PWM output from the FPGA should be interfaced with converter MOSFETgate with proper buffer and MOSFET driver.
• The direct FPGA I/O connection to the MOSFET Gate is not advisable.

Multiphase PWM Signal generation:

• If two or more MOSFETs in the design needs more than one PWM output with different switching phase.
• The above method, generate 'n' number PWMs output with desired phase shift.

Simulation Results:

• Simulation results shows 3 pwm outputs with different duty cycle and different phase shift

Source: eewiki

If you have any questions please email : miycircuits@gmail.com

Job Opening : Hardware Board design Engineer - ATOS

Class 12 : PWM VHDL Code and Simulation Results

PWM VHDL Code and Simulation Results:

• Period is 4 bit variable that defines the ON+OFF cycle time.
• Duty is 4 bit variable define the ON time.
• Duty value shouldn't exceed the period time.
• Until Duty value the PWM will output hig value (Logic 1)
• (Period-duty) value the PWM will output the low value. (Logic 0)

Simulation results:

• Enter the simulation parameters.(Only input variables).
• Clock, duty and period value.
• First simulation results shows duty cycle of 50/50
• Next image shows the PWM output of 20/80 duty cycle

Scope Output:

• Scope output probed @ the FPGA I/O pins. 
• It shows the PWM output of 80/20 duty cycle.

If you have any questions please email : miycircuits@gmail.com

Job Opening - Hardware Development

JOB Opening - Hardware Development 

Class 11 : Converter Design - PWM signal generation

Class 11 : Converter Design - PWM Signal generation 

• In electrical engineering, all power control happens through MOSFET, IGBT, transistor or any switching device. 
• By controlling the ON/OFF period of the switching device we should able to control power flow from the input to the output side load.
• DC-DC converter and AC-DC / DC- AC converters using the switching devices for the power conversion.
• Using the FPGA we should able to control the power converters in open loop and closed loop mode.

• In the given DC-DC converter Close loop control is implemented. 
• Output voltage and current is monitored and controlled through PID control.
• PID control adjust the duty (ON/OFF) of the PWM signal to control the desired output voltage and current. 
• PWM + PID control can be implemented inside the FPGA.

• PWM - Pulse Width Modulation. 
• One cycle of PWM signal having one ON and OFF time period.
• ON (High Period) called as Duty. ON + OFF time called as period.
• Duty cycle define how much percentage of PWM having ON time.

If you have any questions please email us : miycircuits@gmail.com

Class 10 - FPGA Development Board

FPGA Development Board: 

• MiYCircuits developed customized FPGA development for general purpose for learning and project development purpose.

• Development board block diagram. 
• It is available for ordering. Please contact miycircuits@gmail.com

• Feature list for the FPGA development board.

If you have any questions please contact miycircuits@gmail.com

Class 09 : VHDL Programming

VHDL Programming - Basics

• Above list is keywords in VHDL programming. It will be blue color in the program edition.It is not allowed to use the keyword as variable name.

• Example program. Entity part. x,y are single bit input variable.
• Sum, carry is single bit output variable.

• Architecture Body. Half added logic written.

• VHDL program to deine single bit buffer with enable.
• The variable inside process statement is called sensitive variable.
• Any change happening in the sensitive variable will execute the logic. 

If you have any questions please email us : miycircuits@gmail.com

Class 08 - VHDL PROGRAMMING - Basic Only

VHDL Programming: 

• VHDL Program having two blocks. Entity and architecture body.
• Entity block includes the input and output ports used in the program.
• Architecture Body includes the logic.

• Entity is keyword. even_detector is program name. 
• The input and output ports is defined under the port function.
• Input/output can be single or multi bit variable.
• Single bit variable defined as std_logic
• Multi bit variable defined as std_logic_vector(X downto 0)
• Input variable defined as keyword in
• Output variable defined as keyword out

• In the port definition,make sure the output variable is not used for input for the logic.
• In such case, the variable should be defined as signal.

• Architecture body having a program (logic). 
• Local signal declarations can be added.
• Program will be written in between begin and end statement.

Class 07 : Logic Design Process

Logic Design Process:

Synthesis:

Netlist:

Mapping:

Routing:

Programming file:

Logic Design Process by the tool:

• Write the logic in VHDL/Verilog

• Check the syntax.

• Synthesis,placement,routing and generating programming files will be taken care by the software tool provided by Xilinx/Altera.

•  Tool generate the netlist then netlist will be converted in to basic digital elements.

•  Logic elements will be grouped to fit in to the CLB in the placement process.

•  Once placement is done, routing process will make the interconnection between the CLBs.

•  Once routing is complete, the programming file (.bit)will be generated and it will be saved in the  project folder.