Switching Regulator Part -1

Part 1: Why and when to choose Switching Regulator

What is wrong with a linear regulator?

Linear regulators are great for powering very low powered devices. They are easy to use and cheap, and therefore are very popular. However, due to the way they work, they are extremely inefficient.

A linear regulator works by taking the difference between the input and output voltages, and just burning it up as waste heat. The larger the difference between the input and output voltage, the more heat is produced. In most cases, a linear regulator wastes more power stepping down the voltage than it actually ends up delivering to the target device!

With typical efficiencies of 40%, and reaching as low as 14%, linear voltage regulation generates a lot of waste heat which must be dissipated with bulky and expensive heatsinks. This also means reduced battery life for your projects.

Even the new LDO (low drop-out) regulators are still inefficient linear regulators - they just give you more flexibility with input voltage drops.

How is a switching regulator better?

A switching regulator works by taking small chunks of energy, bit by bit, from the input voltage source, and moving them to the output. This is accomplished with the help of an electrical switch and a controller which regulates the rate at which energy is transferred to the output (hence the term “switching regulator”).

The energy losses involved in moving chunks of energy around in this way are relatively small, and the result is that a switching regulator can typically have 85% efficiency. Since their efficiency is less dependent on input voltage, they can power useful loads from higher voltage sources.

Switch-mode regulators are used in devices like portable phones, video game platforms, robots, digital cameras, and your computer.

Switching regulators are complex circuits to design, and as a result they aren’t very popular with hobbyists. However Dimension Engineering creates switching regulators that are even easier to use than linear regulators, because they use the same 3 pin form factor, but don’t require any external capacitors.

What can switching regulators do that linear regulators can't?

With high input voltages, driving loads over 200mA with a linear regulator becomes extremely impractical. Most people use a separate battery pack in these situations, so they have one battery pack for high voltage devices and one for low voltage devices. This means you have twice as many batteries to remember to charge, and twice the hassle! A switching regulator can easily power heavy loads from a high voltage, and save you from splurging on an additional battery pack.

Certain kinds of switching regulators can also step up voltage. Linear regulators cannot do this.

How do I tell if I need a switching regulator?

As a general rule of thumb, if your linear voltage regulation solution is wasting less than 0.5 watts of power, a switching regulator would be overkill for your project. If your linear regulator is wasting several watts of power, you most certainly want to replace it with a switcher! Here is how to calculate power losses:

The equation for wasted power in a linear regulator is:

Power wasted = (input voltage – output voltage) * load current

For example, let’s say you have a 12V lead-acid battery and you want to power a microcontroller that draws 5mA, and an ultrasonic rangefinder that draws 50mA. Both the microcontroller and the ultrasonic rangefinder run off of 5V. You use an LM7805 (a very common linear regulator) to get the voltage down to 5V from 12V.

Power wasted = (12V – 5V) * (0.050A + 0.005A) = 0.385W

0.385W is not too bad for power losses. The LM7805 can handle this without a big heatsink. You could get more battery life if you used a switching regulator, but in this case the power consumption is so low that the battery life will be very long anyway.

Now let’s expand on this example, and add two servos that draw an average of 0.375A each, and also run off of the 5V supply. How much power is wasted in a linear regulator now?

Power wasted = (12V – 5V) * (0.050A + 0.005A + 0.375A + 0.375A) = 5.635W

5.6 Watts is a lot of waste heat! Without a large heatsink the LM7805 would get so hot it would desolder itself or melt your breadboard or defeat Iceman. Even with the heatsink, 5.6W is also a lot of life to suck out of your battery for no reason. 

Is a switching regulator really worth 10+ bucks?

The final thing to consider is of course, cost. If your project is cheap and simple enough that a switching regulator would triple the cost of the entire project, then a switching regulator may be hard to justify. However if you are building a more advanced robot, airplane etc. and a switching regulator adds 15% to your cost, but gives you 35% more battery life, then it is a good deal right?

FPGA Design Interview Questions: - Part 10

FPGA Design Interview Questions: - Part 10

**Entry level FPGA interview questions for 0-3 Exp FPGA Designers**

1. Explain VHDL terms: Configuration, Package, Generic and Process. 

2. Compare Inertial and Transport delay with suitable examples and 
    explain Inertial Delay Model.

3. What is Delta-delay? What is its effect in VHDL? 

4. Differentiate between concurrent and sequential signal assignment 
    statement. State concurrent assignment problem. 

5. Explain data types used in VHDL. List all possible level that can be assigned to 
    std_logic data type. 

6. Design an N-bit parity generator using an XOR gate in a generate statement. 
    Value of N should be passed as a generic parameter with a default value of 8. 
    Use structural modeling style. 

7. Summarize VHDL attributes. What is the use of FOREIGN attribute in VHDL? 

8. Write VHDL code for a priority encoder using 
     (i) Conditional assignment statement 
     (ii) Selected assignment statement 

9. Write a VHDL code to generate clock with ON period of 15 ns and 
     OFF period of 25 ns. 

10. Define function overloading & operator overloading. 

11. Write VHDL code for 1K X 8 RAM with separate input and output buses. 

12. Explain modeling of finite state machines. Also compare Moore state 
      machines and Mealy state machines. 

13. Write the code for an 8-bit Mobius counter. It is an 8-bit shift register where the bits 0  
      and  1 are XOR’ed and fed to the left serial input at the bit 7. The reset signal should 
      initialize  the  counter  to  any  state  other  than  “0000”.  Verify  that  counter  cycles 
      through  15  states  and  then  returns  to  the  initial  state.  Create  a  test  bench  which 
      directly instantiates this counter and generate clock and reset signals. 

14. How to write a test bench? Give typical test bench format. 

15. Design of 8-Nibble ROM using behavior modeling style

16, Design of 8-Nibble RAM using behavior modeling style

17. Design of ODD counter using FSM technique

18. Design of 8 nibble stack using behavior model

19. Design of toggle flip flop using JK flip flop using structural model

20. Design of First -In - First out register using behavior modeling

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FPGA Design Interview Questions: - Part 9

FPGA Design Interview Questions: - Part 9

**Entry level FPGA interview questions for 0-3 Exp FPGA Designers**

1.  Define the following terms:

    1. Configuration declaration in VHDL 2. Transport Delay Model
    3. Sequential Signal assignment statements 4. Component Instantiation

2. Write the VHDL code using structural model for a 9-bit parity generator circuit.

3. List the main purposes of test-bench. Discuss waveform generation using test-bench.

4. Discuss modeling of mealy state machine with suitable example.

5. Do as directed: (1) Differentiate between exit and next statements.
                             (2) Briefly describe necessity of Configuration.
                             (3) Elaborate Package declaration

6. Explain following operators used in VHDL with example
                             (1) rem (2) mod (3) abs

7. Briefly describe implicit and explicit visibility in VHDL.

8. Write a VHDL code using behavioral description for four-bit shift register
      1. Parallel load, 2. Left shift, and 3. Right shift.

9.  Draw a state diagram for Moore type finite state machine (FSM) which
     generates output ‘1’ when it receives input ‘1’ on two subsequent clock cycles.
     Include reset signal which brings FSM to initial state when it goes high. Write
     VHDL code for this FSM using process statement.

10. Explain configuration and package declaration statements using necessary
      examples.

11. Explain various versions of wait statements. What will be the effect of including ‘wait
      for 0 ns’ statement within the middle of process statement which has signal assignments    
      statements before and after this wait statement? Explain with appropriate example.

12. Discuss assertion statement and write a VHDL code for rising edge triggered
      D flip-flop with a check on setup and hold times to demonstrate application of
      this statement.

13. List out uses of block statement and explain each of them in detail with appropriate  
      statements.

14. Explain inertial and transport delay models with necessary examples.

15. Demonstrate the use of generic and FOR-LOOP statements by writing a
      VHDL code for n-input NAND gate.

16. Give general structure of writing a test bench in VHDL. Write a test bench to
      generate D and clock inputs for D flip-flop. Assume VHDL code for D flipflop
      is available. How do you limit simulation time?

17. Write a VHDL program for n-bit adder using structural description by
       instantiating one-bit adder circuit. Program for one-bit adder must be given.

18. Write a behavioral VHDL code for four-bit counter with parallel load. Use
       INTEGER data type for signals.

19. Write a behavioral VHDL code for two-digit BCD counter.

20. List the major capabilities of VHDL along with the features that differentiate
      it from other hardware description languages.

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FPGA Design Interview Questions: - Part 8

FPGA Design Interview Questions: - Part 8

**Entry level FPGA interview questions for 0-3 Exp FPGA Designers**

1.  Define: (1) Delta Delay (2) Transport Delay (3) Routing (4) Placement (5) Postponed 
     Process 

2.  Compare Concurrent Signal Assignment with Sequential Signal Assignment . 

3.  Define  :  Signal  Driver  .  Discuss  effect  of  Transport  Delay  and  Inertial  Delay  on 
     Signal Drivers. Briefly explain Multiple Drivers with it’s problem and solution. 

4.  Discuss any FSM with appropriate example ,State diagram and VHDL code. 

5.  List All Data types of VHDL. Explain Scalar Types with syntax and example. 

6.  Briefly explain All Predefined Operators of VHDL with necessary Example. 

7.  Write a VHDL code for 4 bit Full adder with neat circuit Diagram ,Truth Table and 
     Waveforms 

8.  Write  a  VHDL  code  for  Ripple  counter(Modulo  –  16)  counter  with  neat  Circuit 
      Diagram, Truth table and waveforms. 

9.  Write  a  VHDL  code  for  2  x  4  Decoder  using  Behavioral  and  Structural  style  of 
     modeling. Also draw it’s Circuit Diagram and Truth Table. 

10. Write  a  VHDL  code  for  9  bit  Parity  Generator  with  Circuit  Diagram  and  logic 
       equation. 

11. List down the advantages and disadvantages of Finite State Machines. 

12. Define Mealy State Machine and Moore State Machine.Compare them. 

13. Explain Process statement. Explain the importance of sensitivity list. Quote suitable 
      example. 

14. Explain basic data types in VHDL. 

15. Explain Assertion statement. Explain its usefulness in writing testbench. 

16. What do you mean by Delta-delay ? Also explain Inertial Delay model and Transport 
      Delay model. 

17. Write a short note on operators used in VHDL. 

18. Write the VHDL code for the 4 to 16 decoder using behavioral style of modeling.  

19. Explain Inertial Delay model with suitable example. Also summaries effect of Inertial 
      Delay on Signal Drivers. 

20. (1) Compare Signal and Variable in VHDL (2) Discuss Block statement in VHDL 

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FPGA Design Interview Questions: - Part 7

FPGA Design Interview Questions: - Part 7

**Entry level FPGA interview questions for 0-3 Exp FPGA Designers**


Program1:     Write a VHDL code for frequency divider by 2 

Program2:     Write a VHDL code for frequency divider by 16 

Program3:     Write a VHDL code for frequency divider by 10 

Program4:     Write a VHDL code for frequency divider by 10 using integer counter.

Program5:     Write a VHDL code to  generate 00 to 99 counter with asynchronous reset. 

Program6:     Write a VHDL code for LED chaser for 8 LED's. 

Program7:     Write a VHDL code for BCD to 7 segment Driver.

Program8:     Write a VHDL code for Stepper motor driver- Half step

Program9:     Write a VHDL code for Stepper motor driver - full step

Program10:    Write a VHDL code for timer based traffic light controller

Program11:    Write a VHDL code for sensor based traffic light controller

Program12:    Write a VHDL code for 2:1 mux using stuctural model

Program13:    Write a VHDL code for 4 bit adder using stuctural model

Program14:    Write a VHDL code for 4 bit adder using xor gate

Program15:    Write a VHDL code for 4 bit 2:1 mux using structural model

Program16:    Write a VHDL code for ALU using structural model

Program17:    Write a VHDL code for 4 bit serial In - Parallel out shift register

Program18:    Write a VHDL code for 4 bit parallel in - Parallel out shift register

Program19:    Write a VHDL code for 4 bit serial In - serial out shift register

Program20:    Write a VHDL code for 4 bit stack design using structural modelling

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FPGA Design Interview Questions: - Part 6

FPGA Design Interview Questions: - Part 6

**Entry level FPGA interview questions for 0-3 Exp FPGA Designers**

Program1:     Write a VHDL code for 4:1 Multiplexer using case. 

Program2:     Write a VHDL code for 1:4 Demultiplexer using case

Program3:     Write a VHDL code for 8:3 Encoder using case 

Program4:     Write a VHDL code for 3:8 Decoder using case 

Program5:     Write a VHDL code for 3 bit comparator using if-else

Program6:     Write a VHDL code for BINARY TO GRAY converter using if-else

Program7:     Write a VHDL code for GRAY TO BINARY converter using case

Program8:     Write a VHDL code for D latch with enable pin using if-else

Program9:     Write a VHDL code for SR Latch with enable pin using if-else

Program10:    Write a VHDL code for D-latch with enable pin using case

Program11:    Write a VHDL code for SR Latch with enable pin using case

Program12:    Write a VHDL code for D flip flop with asynchronous reset using if-else

Program13:    Write a VHDL code for D flip flop with synchronous reset using if-else

Program14:    Write a VHDL code for SR flip flop with asynchronous reset using if-else

Program15:    Write a VHDL code for SR flip flop with synchronous reset using if-else

Program16:    Write a VHDL code for JK flip flop with asynchronous reset using if-else

Program17:    Write a VHDL code for JK flip flop with synchronous reset using if-else

Program18:    Write a VHDL code for 2 Bit counter

Program19:    Write a VHDL code for 4 bit counter with asynchronous reset


Program20:    Write a VHDL code for BCD up counter with asynchronous reset

FPGA Design Interview Questions: - Part 5

FPGA Design Interview Questions: - Part 5

**Entry level FPGA interview questions for 0-3 Exp FPGA Designers**

Program1:      Write a VHDL code for 4:1 Multiplexer using When-else.

Program2:      Write a VHDL code for a 1:4 Demultiplexer using when-else.

Program3:      Write a VHDL code for a 8:3 Encoder using When-else.

Program4:      Write a VHDL code for a 3:8 Decoder using When-else.

Program5:      Write a VHDL code for 8:3 Encoder with Priority using when-else.

Program6:      Write a VHDL code for BINARY to GRAY Converter using with-select.

Program7:      Write a VHDL code for GRAY to BINARY Converter using with-select.

Program8:      Write a VHDL code for BINARY to GRAY Converter using when-else.

Program9:      Write a VHDL code for GRAY to BINARY Converter using when-else.

Program10:     Write a VHDL code for BINARY to EXCESS-3 using With-select.

Program11:     Write a VHDL code for BINARY TO GRAY Converter using equation.

Program12:     Write a VHDL code for GRAY to BINARY Converter using equations.

Program13:     Write a VHDL code for Full adder using if-else.

Program14:     Write a VHDL code for Full subtractor using if-else.

Program15:     Write a VHDL code for 4:1 Multiplexer using if-else.

Program16:     Write a VHDL code for 1:4 Demultiplexer using if-else.

Program17:     Write a VHDL code for a 8:3 Encoder using if-else.

Program18:     Write a VHDL code for a 3:8 Decoder using if-else.

Program19:     Write a VHDL code for Full adder using case.HDL code for BINARY TO EXCESS-3
                        using equations.

Program20:     Write a VHDL code for Full subtractor using case. 

FPGA Design Interview Questions: - Part 4

FPGA Design Interview Questions: - Part 4

**Entry level FPGA interview questions for 0-3 Exp FPGA Designers**

Program-1: Write a VHDL Program for all Logic Gates.

Program-2: Write a VHDL code for a Half Adder

Program-3: Write a VHDL code for a Full Adder

Program-4: Write a VHDL code for a Half Subtractor

Program-5: Write a VHDL code for a Full Subtractor

Program-6: Write a VHDL code for a 4:1 Multiplexer

Program-7: Write a VHDL code for a 1:4 Multiplexer

Program-8: Write a VHDL code for a 4:2 Encoder

Program-9: Write a VHDL code for a 2:4 Decoder

Program-10:Write a VHDL code for 1 bit Comparator

Program-11 : Write a VHDL code for all gates using with-select.

Program-12: Write a VHDL code for Full adder using with-select.

Program-13: Write a VHDL code for Full subtractor using with-select.

.
Program-14: Write a VHDL code for 4:1 Multiplexer using With-select.

Program-15: Write a VHDL code for a 1:4 Demultiplexer using with-select.

Program-16: Write a VHDL code for a 8:3 Encoder using With-Select.

Program-17: Write a VHDL code for a 3:8 Decoder using With-Select.

Program-18 : Write a VHDL code for all gates using when-else.

Program-19: Write a VHDL code for Full adder using when-else.

Program-20: Write a VHDL code for Full subtractor using when-else.3: Write a VHDL code for Full subtractor using with-select

FPGA Design Interview Questions: - Part 3

FPGA Design Interview Questions: - Part 3

**Entry level FPGA interview questions for 0-3 Exp FPGA Designers**

41. Write the generic initialization sequences involved on 16x2 LCD interface?

42. What is the role of LCD_RS signal?

43. Explain is UART interface? Applications of UART?

44. What is the maximum distance we can connect using UART interface?

45. What is Baud rate?

46. Explain signal framing in UART protocol?

47. How the data is transmitted through the UART?Timing diagram ?

48. What is the 8B/10B encoding?

49. Define Mealy State Machine and Moore State Machine. Compare them?

50. Explain Process statement in VHDL programming ?

51. Explain the importance of sensitivity list ? Give the example.

52. Basic datatypes in VHDL ?

53. What is delta delay and transport delay ?

54. Explain the routing and placement process in Xilinx ISE tool ?

55. Compare concurrent signal assignment with sequential signal assignment ?

56. List all the data types in VHDL and explain Scalar type ?

57. Explain predefined operator with examples ?

58. Write the Code for 4 bit full adder ?

59. Write the VHDL code for 2x4 decoder ?

60. Write the VHDL code for 9 bit parity generator ?

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FPGA Design Interview Questions: - Part 2

FPGA Design Interview Questions: - Part 2

**Entry level FPGA interview questions for 0-3 Exp FPGA Designers**

21. What is skew in the digital signal transmission ?

22. What is clock skew and explain the types ?

23. How push-pull driver works?

23. What is open drain or open collector output and draw the circuit?

24. What is RACE AROUND condition?

25. Difference between Crystal and Oscillator?

26. Difference between DRAM and BRAM?

27. List the different type of memories used ?

28. Draw a simple circuit to LED ?

29.Explain LOW- DROPOUT regulator circuit ?

30. What is the role of reset in digital design ?

31. why ACTIVE LOW RESET is used mostly in the design ?

32.Explain difference between LDO AND SWITCHING REGULATOR ?

32. What is Switching Frequency and the importance ?

33. Benefits of High Switching Frequency?

34. Drawbacks of High Switching Frequency?

35. Explain the duty cycle and the role?

36. Draw a simple circuit to interface PWM signal into a MOSFET?

37. What is linear region operation of MOSFER ? Draw characteristics ?

38. Explain the saturation region operation of the MOSFET ?

39. Draw a simple circuit to connnect pwm from the FPGA to a MOSFET?

40. Explain the operation of MOSFET driver circuits ?

FPGA Design Interview Questions- Part 1

FPGA Design Interview Questions:

**Entry level FPGA interview questions for 0-3 Exp FPGA Designers**

1. What are the applications of FPGA?

2. Difference between FPGA and micro controller?

3. Difference between fpga and DSP or microprocessor?

4. Difference between FPGA and CPLD?

5. Why prefer FPGA over CPLD?

6. What are the types of FPGA available?

7. Why FPGA are re-configurable?

8. What are the generic internal blocks of FPGA?

9. What are the internal blocks of CLB?

10. What is LUT?

11. Truth table for logic gates?

12. Describe 4-input mux?

13. Explain encoder and decoder?

14. What are the steps involved to create programming file?

15. Difference between VHDL and verilog programming language?

16. Internal steps to synthesize and implement design?

17. Implementation of simple flip flop’s in VHDL code?

18. Write VHDL coding for 4-input mux?

19. Explain about Single ended signals and differential ended signals?

20. Difference between single and differential ended signals?

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Linear Regulator FAQ

Linear Regulator – FAQ:

What are the typical applications for a low-dropout (LDO) linear regulator?

LDO linear regulators usually are employed in systems that require a low-noise power source instead of a switching regulator that might upset the system. LDOs also find use in applications where the regulator must maintain regulation with small differences between the input supply voltage and output load voltage, such as battery-powered systems. Their low dropout voltage and low quiescent current make them a good fit for portable and wireless applications.

How much output current can an LDO provide?

LDOs with an on-chip power MOSFET or bipolar transistor typically provide outputs in the 50to 1000-mA range.

What is a typical LDO regulator circuit?

An LDO voltage regulator operates in the linear region with the topology shown in the figure. As a basic voltage regulator, its main components are a series pass transistor (bipolar transistor or MOSFET), differential error amplifier, and precise voltage reference.

What characteristics affect an LDO's performance?

The key operational factors for an LDO are its dropout voltage, power-supply rejection ratio, output noise, and quiescent current.

What is dropout voltage?

Low dropout refers to the difference between the input and output voltages that allow the IC to regulate the output load voltage. That is, an LDO can regulate the output load voltage until its input and output approach each other at the dropout voltage. Ideally, the dropout voltage should be as low as possible to minimize power dissipation and maximize efficiency. Typically, dropout is considered to be reached when the output voltage has dropped to 100 mV below its nominal value. The load current and pass transistor temperature affect the dropout voltage.

What is power-supply ripple rejection?

Power-supply ripple rejection (PSRR) affects the LDO's ability to prevent output voltage fluctuations caused by variations in input voltage. PSRR is usually specified at a specific frequency, for example, 60-dB rejection at 120 Hz. Low-ESR (equivalent series resistance) output capacitors and added reference voltage bypass capacitors improve the PSRR performance. Battery-based systems should employ LDOs that maintain high PSRR at low battery voltages.

What affects an LDO's output noise?

An LDO's internal voltage reference is a potential noise source, usually specified as microvolts rms over a specific bandwidth, such as 30 µV rms from 1 to 100 kHz. This low-level noise causes fewer problems than the switching transients and harmonics from a switch-mode converter. In the figure, the LDO has a (voltage-reference) bypass pin to filter reference voltage noise with a capacitor to ground. Adding the datasheet-specified input, output, and bypass capacitors usually results in a non-problematic noise level.

What is quiescent current?

Another important characteristic is the quiescent or ground current (the current flowing through the system when no load is present), which creates a difference between the input and output currents. The series pass element, topologies, and ambient temperature are the primary contributors to quiescent current. Quiescent current and input to output voltage limit LDO efficiency and should be minimized.

How does the output capacitor affect LDO performance?

Controlling the LDO's frequency compensation loop to include the load capacitor reduces sensitivity to the capacitor's ESR, which allows a stable LDO with good quality capacitors of any type. In addition, output capacitor placement should be as close as possible to the output.

What circuit features can enhance LDO performance?

An enable input permits external control of LDO turn-on and turn-off, which allow the sequencing of supplies in multirail systems. Soft-start limits inrush current and controls output voltage rise time during power-up. A sleep state minimizes power, particularly in battery-based systems. A bypass pin enables an external capacitor to reduce reference voltage noise. An error output indicates if the output is going out of regulation, also known as a voltage-good or power-good output. Thermal shutdown turns the LDO off if its temperature exceeds the specified amount. Overcurrent protection (OCP) limits the LDO's output current and power dissipation. And, another important feature available in the latest generation of LDOs is voltage tracking, which enables controlled sequencing of multiple LDOs powering multiple supply sensitive digital loads (e.g., an IC with an I/O and a core voltage requirement).

What factors determine the optimum LDO for a specific application?

Considerations include the type and range of the applied input voltage, required output voltage, maximum load current, minimum dropout voltage, quiescent current, power dissipation, and shutdown current.

How does output-capacitor ESR affect LDO performance?

The output capacitor's ESR can affect LDO control loop stability. For example, a minimum of 1µF capacitance with an ESR of 500 mW or less is usually recommended to ensure the stability of a CMOS LDO. Transient response to changes in load current is also affected by output capacitance. Plus, using a larger value of output capacitance improves the transient response of the LDO to large changes in load current.

What type of output capacitors should be employed with an LDO?

Any ceramic capacitors that are of good quality can be used with most LDOs, as long as they meet the minimum capacitance and maximum ESR requirements. Ceramic capacitors are manufactured with a variety of dielectrics, each with different behavior over temperature and applied voltage. Capacitors must have a dielectric adequate to ensure the minimum capacitance over the necessary temperature range and dc bias conditions. X5R or X7R dielectrics with a voltage rating of 6.3 V or 10 V are recommended. Y5V and Z5U dielectrics are not recommended, due to their poor temperature and dc bias characteristics.

What is the effect of the input bypass capacitor?

Connecting a 1-µF capacitor from input to ground reduces the circuit sensitivity to printed-circuit-board (PCB) layout, especially when long input traces or high source impedances are encountered. If greater than 1 µF of output capacitance is required, the input capacitor should be increased to match it.

Linear Regulator Lessons End Here. Please email if you have any feedback.

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Linear Regulator Part 13 Selection Criteria

Linear Regulator Selection Criteria:

• V_IN (min)
• V_IN (max)
• V_OUT
• I_OUT
• Power Dissipation
• Dropout Voltage
• PSRR
• Ultra Low I_Q

V_IN (min)

• Is your input voltage able to drive the pass-element of LDO?
  • V _IN (min) > 2.5V : PMOS-type LDOs
  • V _IN (min) > 1.0V : NMOS-type LDOs with voltage bias or internal charge pump

V_IN (min)

Is your input voltage able to drive the pass-element of LDO?

• V _IN (min) > 2.5V : PMOS-type LDOs
• V _IN (min) > 1.0V : NMOS-type LDOs with voltage bias or internal charge pump

V_IN (max)

Which upper bound of input voltage fits for your application best?

V_OUT

Do you need an adjustable output voltage? Which method do you prefer?

Fixed output voltage LDOs have the feedback network internally. Adjustable output LDOs use an external feedback network, which gives more flexibility. Some adjustable parts also have an internal feedback network, so they can be used as fixed output version as well.

I_OUT

What is the current requirement of your application?

The current capability relates directly to dropout voltage and power dissipation.

LDO controllers use external MOSFETs which can have larger current capability.

Power Dissipation

The power dissipation in the LDO is determined by the voltage drop (V_IN-V_OUT) across the LDO multiplied by the current passing through the LDO (I_OUT), which can be calculated from the formula P_D = (V_IN - V_OUT) * I_LOAD.

The below graph shows the allowed LDO voltage drop versus LDO current for specific power dissipation values.

Larger current or larger voltage drop across the LDO quickly leads to high device power dissipation. The LDO package needs to be able to handle this power dissipation.

Maximum allowed device power dissipation for SMD type LDOs depends on package, PCB layout and ambient temperature. You can calculate the allowed power dissipation by dividing the allowed temperature difference between junction and ambient by the thermal resistance between junction and ambient. The thermal resistance value θ_JA is shown in the datasheet, but keep in mind that this value is based on the JEDEC method, which can be slightly conservative.

Here are some practical power dissipation limits for various package types, based on a normal PCB layout with some extra copper connected to the package pins and thermal pad, a maximum PCB ambient temperature of 60°C, and maximum silicon die temperature of 125°C. If your ambient temperature is lower, the power dissipation can be higher. If your PCB is small, or there are other hot components nearby, the maximum power dissipation may be less.

Dropout Voltage

LDOs need a certain minimum voltage drop to regulate correctly.

 LDOs are Low Dropout Linear regulators. It basically means that these devices can still regulate the output voltage, even when the input voltage is very close to the output voltage.

LDO dropout voltage is defined as the voltage drop across the regulator where the device can no longer regulate the output voltage.

Here is the basic circuit of an LDO with a P-channel MOSFET pass device. The MOSFET source is connected to VIN. To regulate the output voltage, the error amplifier controls the P-MOSFET gate voltage with respect to VIN, thereby controlling the MOSFET conduction level.

The LDO needs a certain amount of input to output voltage difference for regulation.

When the difference between input and output voltage becomes smaller, the MOSFET operation shifts toward the MOSFET Ohmic region toward the left in the MOSFET I/V curves.

In the Ohmic region, the MOSFET becomes resistive, and the error amplifier will pull the gate near ground level. At that point, the output voltage cannot be regulated anymore.

To maintain a well regulated LDO output voltage, you should make sure that the input voltage including ripple and tolerances is always higher than the output voltage + LDO dropout voltage.

Dropout curves as shown in the LDO datasheet show this dropout voltage as a function of output current and temperature.

These I/V curves basically represent the R _DS(ON) of the pass MOSFET.

PSRR

PSRR stands for power supply ripple rejection. The LDO PSRR value quantifies how well the LDO can reject input supply ripple at a certain frequency to keep the output voltage free of noise and ripple. In datasheets, PSRR is defined as the ripple attenuation ratio V_OUT/V_IN, therefore lower PSRR values are better.

The diagram shows the example of PSRR vs. frequency. At frequencies up to 10kHz, LDOs have high open loop gain, and can reject input ripple very well.

When frequency increases, the loop gain reduces due to the bandwidth limit of the LDO, and the PSRR curves rise. Higher LDO load pushes the load pole upwards, so the unity gain frequency at high load is also higher. In this example the LDO unity gain frequency is 300kHz at light load and 1MHz at high load, as can be seen from the peaks in the graph.

Above the unity gain frequency, the LDO is not able to actively remove ripple. The ripple attenuation at these very high frequencies is mostly caused by the LDO output capacitor and the LDO internal parasitic impedance.

Ultra Low Quiescent Current (I_Q)

Does your application need to run from a small battery cell for long periods?

These applications often will run in sleep mode most of the time, and are only active for short periods. To minimize the power consumption in sleep mode, you need to select parts with very low quiescent current.

The LDO quiescent current is the current that is consumed by the IC internal feedback control and drive circuits. It is normally measured by measuring the current that flows out of the LDO ground pin.

Low I_Q LDO portfolio contains LDOs with quiescent currents down to 1μA, which extends battery lifetime considerably.

Ultra low I_Q LDOs provide dynamic quiescent current control for obtaining the best performance in battery powered applications requiring long battery life and good dynamic load performance. The Low I_Q LDO provides a stable 2.8V supply to the micro controller, and the LDO ground current stays relatively constant at 1μA in the low load range, thereby prolonging battery life.

But at higher load currents, the ground current increases to improve the dynamic behavior of the LDO; when a sudden high load is encountered, the internal control circuit uses more energy to ensure a tight regulation of the output voltage.