FPGA Design Interview Questions: - Part 10

FPGA Design Interview Questions: - Part 10

**Entry level FPGA interview questions for 0-3 Exp FPGA Designers**

1. Explain VHDL terms: Configuration, Package, Generic and Process. 

2. Compare Inertial and Transport delay with suitable examples and 
    explain Inertial Delay Model.

3. What is Delta-delay? What is its effect in VHDL? 

4. Differentiate between concurrent and sequential signal assignment 
    statement. State concurrent assignment problem. 

5. Explain data types used in VHDL. List all possible level that can be assigned to 
    std_logic data type. 

6. Design an N-bit parity generator using an XOR gate in a generate statement. 
    Value of N should be passed as a generic parameter with a default value of 8. 
    Use structural modeling style. 

7. Summarize VHDL attributes. What is the use of FOREIGN attribute in VHDL? 

8. Write VHDL code for a priority encoder using 
     (i) Conditional assignment statement 
     (ii) Selected assignment statement 

9. Write a VHDL code to generate clock with ON period of 15 ns and 
     OFF period of 25 ns. 

10. Define function overloading & operator overloading. 

11. Write VHDL code for 1K X 8 RAM with separate input and output buses. 

12. Explain modeling of finite state machines. Also compare Moore state 
      machines and Mealy state machines. 

13. Write the code for an 8-bit Mobius counter. It is an 8-bit shift register where the bits 0  
      and  1 are XOR’ed and fed to the left serial input at the bit 7. The reset signal should 
      initialize  the  counter  to  any  state  other  than  “0000”.  Verify  that  counter  cycles 
      through  15  states  and  then  returns  to  the  initial  state.  Create  a  test  bench  which 
      directly instantiates this counter and generate clock and reset signals. 

14. How to write a test bench? Give typical test bench format. 

15. Design of 8-Nibble ROM using behavior modeling style

16, Design of 8-Nibble RAM using behavior modeling style

17. Design of ODD counter using FSM technique

18. Design of 8 nibble stack using behavior model

19. Design of toggle flip flop using JK flip flop using structural model

20. Design of First -In - First out register using behavior modeling

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