FPGA Design Interview Questions: - Part 9

FPGA Design Interview Questions: - Part 9

**Entry level FPGA interview questions for 0-3 Exp FPGA Designers**

1.  Define the following terms:

    1. Configuration declaration in VHDL 2. Transport Delay Model
    3. Sequential Signal assignment statements 4. Component Instantiation

2. Write the VHDL code using structural model for a 9-bit parity generator circuit.

3. List the main purposes of test-bench. Discuss waveform generation using test-bench.

4. Discuss modeling of mealy state machine with suitable example.

5. Do as directed: (1) Differentiate between exit and next statements.
                             (2) Briefly describe necessity of Configuration.
                             (3) Elaborate Package declaration

6. Explain following operators used in VHDL with example
                             (1) rem (2) mod (3) abs

7. Briefly describe implicit and explicit visibility in VHDL.

8. Write a VHDL code using behavioral description for four-bit shift register
      1. Parallel load, 2. Left shift, and 3. Right shift.

9.  Draw a state diagram for Moore type finite state machine (FSM) which
     generates output ‘1’ when it receives input ‘1’ on two subsequent clock cycles.
     Include reset signal which brings FSM to initial state when it goes high. Write
     VHDL code for this FSM using process statement.

10. Explain configuration and package declaration statements using necessary
      examples.

11. Explain various versions of wait statements. What will be the effect of including ‘wait
      for 0 ns’ statement within the middle of process statement which has signal assignments    
      statements before and after this wait statement? Explain with appropriate example.

12. Discuss assertion statement and write a VHDL code for rising edge triggered
      D flip-flop with a check on setup and hold times to demonstrate application of
      this statement.

13. List out uses of block statement and explain each of them in detail with appropriate  
      statements.

14. Explain inertial and transport delay models with necessary examples.

15. Demonstrate the use of generic and FOR-LOOP statements by writing a
      VHDL code for n-input NAND gate.

16. Give general structure of writing a test bench in VHDL. Write a test bench to
      generate D and clock inputs for D flip-flop. Assume VHDL code for D flipflop
      is available. How do you limit simulation time?

17. Write a VHDL program for n-bit adder using structural description by
       instantiating one-bit adder circuit. Program for one-bit adder must be given.

18. Write a behavioral VHDL code for four-bit counter with parallel load. Use
       INTEGER data type for signals.

19. Write a behavioral VHDL code for two-digit BCD counter.

20. List the major capabilities of VHDL along with the features that differentiate
      it from other hardware description languages.

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