FPGA Design Interview Questions: - Part 3

FPGA Design Interview Questions: - Part 3

**Entry level FPGA interview questions for 0-3 Exp FPGA Designers**

41. Write the generic initialization sequences involved on 16x2 LCD interface?

42. What is the role of LCD_RS signal?

43. Explain is UART interface? Applications of UART?

44. What is the maximum distance we can connect using UART interface?

45. What is Baud rate?

46. Explain signal framing in UART protocol?

47. How the data is transmitted through the UART?Timing diagram ?

48. What is the 8B/10B encoding?

49. Define Mealy State Machine and Moore State Machine. Compare them?

50. Explain Process statement in VHDL programming ?

51. Explain the importance of sensitivity list ? Give the example.

52. Basic datatypes in VHDL ?

53. What is delta delay and transport delay ?

54. Explain the routing and placement process in Xilinx ISE tool ?

55. Compare concurrent signal assignment with sequential signal assignment ?

56. List all the data types in VHDL and explain Scalar type ?

57. Explain predefined operator with examples ?

58. Write the Code for 4 bit full adder ?

59. Write the VHDL code for 2x4 decoder ?

60. Write the VHDL code for 9 bit parity generator ?

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