FPGA Design Interview Questions: - Part 6

FPGA Design Interview Questions: - Part 6

**Entry level FPGA interview questions for 0-3 Exp FPGA Designers**

Program1:     Write a VHDL code for 4:1 Multiplexer using case. 

Program2:     Write a VHDL code for 1:4 Demultiplexer using case

Program3:     Write a VHDL code for 8:3 Encoder using case 

Program4:     Write a VHDL code for 3:8 Decoder using case 

Program5:     Write a VHDL code for 3 bit comparator using if-else

Program6:     Write a VHDL code for BINARY TO GRAY converter using if-else

Program7:     Write a VHDL code for GRAY TO BINARY converter using case

Program8:     Write a VHDL code for D latch with enable pin using if-else

Program9:     Write a VHDL code for SR Latch with enable pin using if-else

Program10:    Write a VHDL code for D-latch with enable pin using case

Program11:    Write a VHDL code for SR Latch with enable pin using case

Program12:    Write a VHDL code for D flip flop with asynchronous reset using if-else

Program13:    Write a VHDL code for D flip flop with synchronous reset using if-else

Program14:    Write a VHDL code for SR flip flop with asynchronous reset using if-else

Program15:    Write a VHDL code for SR flip flop with synchronous reset using if-else

Program16:    Write a VHDL code for JK flip flop with asynchronous reset using if-else

Program17:    Write a VHDL code for JK flip flop with synchronous reset using if-else

Program18:    Write a VHDL code for 2 Bit counter

Program19:    Write a VHDL code for 4 bit counter with asynchronous reset


Program20:    Write a VHDL code for BCD up counter with asynchronous reset