FPGA Design Interview Questions: - Part 8

FPGA Design Interview Questions: - Part 8

**Entry level FPGA interview questions for 0-3 Exp FPGA Designers**

1.  Define: (1) Delta Delay (2) Transport Delay (3) Routing (4) Placement (5) Postponed 
     Process 

2.  Compare Concurrent Signal Assignment with Sequential Signal Assignment . 

3.  Define  :  Signal  Driver  .  Discuss  effect  of  Transport  Delay  and  Inertial  Delay  on 
     Signal Drivers. Briefly explain Multiple Drivers with it’s problem and solution. 

4.  Discuss any FSM with appropriate example ,State diagram and VHDL code. 

5.  List All Data types of VHDL. Explain Scalar Types with syntax and example. 

6.  Briefly explain All Predefined Operators of VHDL with necessary Example. 

7.  Write a VHDL code for 4 bit Full adder with neat circuit Diagram ,Truth Table and 
     Waveforms 

8.  Write  a  VHDL  code  for  Ripple  counter(Modulo  –  16)  counter  with  neat  Circuit 
      Diagram, Truth table and waveforms. 

9.  Write  a  VHDL  code  for  2  x  4  Decoder  using  Behavioral  and  Structural  style  of 
     modeling. Also draw it’s Circuit Diagram and Truth Table. 

10. Write  a  VHDL  code  for  9  bit  Parity  Generator  with  Circuit  Diagram  and  logic 
       equation. 

11. List down the advantages and disadvantages of Finite State Machines. 

12. Define Mealy State Machine and Moore State Machine.Compare them. 

13. Explain Process statement. Explain the importance of sensitivity list. Quote suitable 
      example. 

14. Explain basic data types in VHDL. 

15. Explain Assertion statement. Explain its usefulness in writing testbench. 

16. What do you mean by Delta-delay ? Also explain Inertial Delay model and Transport 
      Delay model. 

17. Write a short note on operators used in VHDL. 

18. Write the VHDL code for the 4 to 16 decoder using behavioral style of modeling.  

19. Explain Inertial Delay model with suitable example. Also summaries effect of Inertial 
      Delay on Signal Drivers. 

20. (1) Compare Signal and Variable in VHDL (2) Discuss Block statement in VHDL 

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