FPGA Design Interview Questions: - Part 4

FPGA Design Interview Questions: - Part 4

**Entry level FPGA interview questions for 0-3 Exp FPGA Designers**

Program-1: Write a VHDL Program for all Logic Gates.

Program-2: Write a VHDL code for a Half Adder

Program-3: Write a VHDL code for a Full Adder

Program-4: Write a VHDL code for a Half Subtractor

Program-5: Write a VHDL code for a Full Subtractor

Program-6: Write a VHDL code for a 4:1 Multiplexer

Program-7: Write a VHDL code for a 1:4 Multiplexer

Program-8: Write a VHDL code for a 4:2 Encoder

Program-9: Write a VHDL code for a 2:4 Decoder

Program-10:Write a VHDL code for 1 bit Comparator

Program-11 : Write a VHDL code for all gates using with-select.

Program-12: Write a VHDL code for Full adder using with-select.

Program-13: Write a VHDL code for Full subtractor using with-select.

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Program-14: Write a VHDL code for 4:1 Multiplexer using With-select.

Program-15: Write a VHDL code for a 1:4 Demultiplexer using with-select.

Program-16: Write a VHDL code for a 8:3 Encoder using With-Select.

Program-17: Write a VHDL code for a 3:8 Decoder using With-Select.

Program-18 : Write a VHDL code for all gates using when-else.

Program-19: Write a VHDL code for Full adder using when-else.

Program-20: Write a VHDL code for Full subtractor using when-else.3: Write a VHDL code for Full subtractor using with-select